1/9 AN829 application note november 2003 boost circuit optimization parameters among the available topologies, a boost circuit operating in continuous current mode is the only topology which enables the rfi noise across the input capacitor to be limited, and consequently a lower cost filter is required. also, the boost inductor stores only a part of the transferred energy, because the mains st ill s upplies energy during the demagnetization phase of the boost inductor - so the magnetic part required is smaller than needed with any other topology. therefore the boost topology leads to the cheapest solution. figure 1 shows the general topology of a boost pfc. its optimization requires careful adjustment of the following parameters: C the value of the input capacitor c i C the current ripple in the boost inductor l b C the parasitic capacitances of the boost inductor and power semiconductors, including those associ- ated with the heatsink C the operating frequency and also the frequency modulation technique. figure 1. semiconductor kit for pfc schematic. + c1 lb sth80n05 ste30na50-dk lp1 1/ky 7 6 13 + - 14 vref lp5 lp2 x lp3 lp4 + - a + - freq. modul.(b) synchron. (a) 89 10 5 + 20 full protection one chip l4981a/b controller 4 any compensation 1 d95in252a by j.m. borgeous semiconductor kit for power factor corrector this paper present a new line of p.f.c. dedicated products. both silicon and packaging have been op- timized to reduce system cost, including filtering. the products shown here are offered as a kit for power factor correction.
AN829 application note 2/9 semi-conductor kit the semiconductor kit consists of an l4981 controller, an ste36n50-dk power module and an sth80n05 power sense (see figure 1). l4981a/b controller: the l4981 operates with an input voltage range of 85v to 270v and uses average current mode pwm control, providing feed forward line and load compensation. two versions are available: version (a) provides synchro- nization with the down stream converter, whereas version (b) provides linear frequency modulation, spreading the rfi noise spectrum. both versions incorporate overvoltage and overcurrent protection, soft start and under voltage lockout with pro- grammable threshold. other features include an on chip voltage reference (2%) which is externally available, a typical starting current of only 0.5ma and separate grounds for the power and signal stages. l4981 use an optimum current control method. it is an average current control using feed forward line regulation and variable or fixed switching frequency. the oscillator simultaneously turns on the power switch and starts the ramp of the pwm current control. the average inductor current is compared with the current reference by means of the current error amplifier. it op- erates as an integrator, allowing the circuit to accurately follow the current reference generated by the multiplier. this current reference is obtained by sinewave modulating the error voltage of the voltage control loop. a feed forward compensation of the mains voltage has been added to the multiplier in order to keep constant the voltage control loop bandwidth whatever the mains fluctuation. a fourth multiplier input allows external com- pensation to be applied to the current modulation. the oscillator can operate at constant or modulated switching frequency. in applications where modulated fre- quency is used, the rfi noise spectrum can be spread adjusting the depth of modulation by means of an exter- nal resistor. then the maximum inductor current occurs at the minimum operating frequency. ste30na50-dk power module: built in an isolated isotop tm package, which can be mounted directly on a pcb, this module integrates a low r ds(on) power mosfet and a turboswitch tm diode. putting these two components in a single isolated package with very low parasitic inductance and capacitance reduces the component count, and significantly re- duces transient overvoltages, and emi and rfi. as a result, the design safety margin can be relaxed and the voltage rating of the power mosfet can be just 500v (br)dss , meaning also that the r ds(on) of the mosfet can be lower - in this case it is 0.14 ohm. both the current and avalanche handling capab ilities of the power mosfet section are specified at 100c junction tem- perature, allowing for maximum utilization of the device. the mosfet is a low gate-charge type and so its drive requirements are compatible with the 2a peak current capability of the l4981 controller. the integrated turboswitch tm freewheeling diode is an ultra-fast, soft recovery device using planar epitax- ial technology, and is a part of the stta series. its low trr (30ns) keeps the mosfet switching losses to a min- imum. other ratings are 600v rrm and a maximum v f of 1.5v at the rated average forward current (i fav = 20a). sth80n05 power sense: using a high density low voltage power mosfet for current sensing has many advantages: C low resistance, typically 10m2
3/9 AN829 application note C can be mounted on the same heatsink as the isotop C intrinsic diode for controller input protection C very low parasitic inductance improving signal/noise ratio. however, the peak current limitation will be affected by the mosfet thermal characteristic. design rule example taking the following operating conditions (see figure 2): v in rms = 230vac +10% -15% (f=50hz) i in rms = 16arms p out = 3000w v out = 400vdc or v in rms = 120vac +20% -20% (f=60hz) i in rms = 15arms p out = 1400w v out = 400vdc figure 2. 1500w/3000w pfc schematic. l4981 r20 19 lb 95 c p r z 1 r gf 20 c18 r17 c12 12 17 18 f1 d95in253a c1 + - + - r19 d2 dz c z 611 d gf turboswitch diode 1 j1 1 j2 d1 c19 q1 sth80n05 r16 r8 r9 8 r4 r71 r72 r73 c72 c71 r gn 10 isotop ste30na50-dk c o10 to c o14 c o2 to c o7 j7 1 1 j8 r141 r142 r14 r31 r32 14 3 r13 c13 13 sgnd pgnd vfeed vaout vp gdrv caout isense vcc mout iac vrms ssc cosc rosc 16 r2 2 ipk lff vref s/fm 4 7
AN829 application note 4/9 component list 1 1 c1 10 m f/250vac 2 6 co2,co3,co4,co5,co8,co7 330 m f/450v 3 5 co10,co11,co12,co13,co14 0.33 m f/450v 4 1 cp tbd 5 1 cz 150pf/100v 6 2 c12, c72 1 m f/100v 7 1 c13 22nf/100v 8 1 c18 2.2nf/100v 9 1 c19 220 m f/25v 10 1 c71 68nf/100v 11 1 diode turboswitch 12 1 dgf byw100 13 1 d1 regular diode bridge or 2xmds35 14 1 d2 4 x byw100 15 1 f1 3ag fuse 16 1 isotop ste36n50dk 17 2 j2, j1 con5 18 2 j7, j8 con2 19 1 laux auxiliary winding 20 1 lb boost inductor 21 1 q1 sth80n05 22 1 rgf 1 1/4w 23 1 rhn 4.7 1/2w 24 2 r72, rz 100k 1/4w 25 2 r142, r2 10k 1/4w 26 2 r31, r4 1m 1/4w 27 1 r8, r9 4k 1/4w 28 1 r13 390k 1/4w 29 1 r14 47k 1/4w100k 30 1 r16 no r16 with l4981a 31 1 r17 24k 1/4w 32 1 r19 47 1w 33 1 r20 100k 2w 34 1 r32 4.7k 1/4w 35 1 r71 820k 1/4w 36 1 r73 22k 1/4w 37 1 r141 750k 1/4w 38 1 u1 l4981a/b
5/9 AN829 application note switching frequency fs is kept below 50khz to maintain the rfi noise within the optimum frequency range of the vfg 243 standard. figure 3 shows that in the range of 10khz/50khz the switching frequency fun- damental spectrum requires less filtering. c18 = 2.2nf and r17 = 24k2 give a switching frequency of 46khz. boost inductor: for applications in the range of 3kw, the boost inductor design is greatly determined by material choice and core availability. as mentioned the inductor parasitic capacitance determines the filter requirements in the range 1mhz-30mhz (with regards to the switching noise). to keep this capacitance as low as possible, a single layer winding is the best solution, but this requires the use of a toroidal core shape to balance winding turns and core section. in this case a material with distributed air gaps, for example iron powder, is a good choice (see #2). this is the cheapest core material available with an inherently high saturation flux density combined with a dis- tributed air gap. test have been performed using two different cores: C t300-26d core from micrometal (anaheim, ca) made of iron powder / 60 turns / 12 awg. C 2 x co55866a2 core from magnetics, made of nickel, iron and molybdenum / 46 turns / 12 awg. output capacitance value depends upon the expected output voltage drop during the specified holdup time. considering a value of 2000f, the voltage drop during a 10msec holdup can be calculated from: pout 10msec = 1/2 cout (vout - vmin) then v min = 382v at 1400w and v min = 360v at 3000w feed forward compensation: pin 7 should be supplied with a voltage proportional to the rms mains voltage. this voltage must be in the range of 1.5v to 5.5v. the circuit shown in figure 4 gives a good compromise between response time and harmonic attenuation with the following values: c71=68nf, c72 = 1mf, r71=820k w , r72 =1 00k w and r73 = 22k w . figure 3. vfg 243 limits figure 4. feed forward compensation net- work 100 90 80 70 60 50 40 50 khz 150 khz 500 khz 10 khz 30 mhz d95in254 approximate vfg243 limits r71 r72 c71 c72 r73 7 rectified mains voltage d95in255
AN829 application note 6/9 voltage error amplifier: operating with p out = 3000w and v out = 400vdc, the mean i out is 7.5a. the corresponding 100hz capacitor cur- rent is defined by: i capa = (p out / v out ) cos 4!ft so the peak current is: p out/ v out = 7.5a then the output voltage ripple v r can be evaluated as: v r = 7.5a / 2 p 100 3500 e-6 = 6vpeak voltage divider r141/r142 attenuates the output voltage ripple to: v ri = 6vpeak x 5.1/400 = 0.0765vpeak assuming 3% peak voltage ripple at the voltage error amplifier output, ripple can be evaluated as: vro = (5.1v - 1.27v) 0.03 = 0.115vpeak where the first term is the output error amplifier voltage range. then the global voltage error amplifier gain at 100hz must be: g vea = v ro /v ri = 0.115/0.0765 = 1.5 as g vea # 1 / r14 2 p f c13 with r14 = 47k w then c13=22nf to maintain voltage loop stability requires the placement of a pole at a unity-gain frequency of about 18hz (see #5) then r13c13 = 1/2 p . 18 and r13 = 390k w load compensation: a voltage applied at pin 6 can be used to perform compensation, for example a load feed forward compensation. with reference to the multiplier section, this input is equivalent to the voltage error amplifier output. if not used, it should be connected to the reference voltage (pin 11). multiplier circuit has the following response: imult = k mult iac (v vea -1.27) (0.8lff-1.27)/vrms where: k mult is the multiplier constant (.37) v vea is the voltage error amplifier output. lff is the voltage at pin 6. iac is the current supplied into pin 4. vrms is voltage at pin 7. to keep the maximum multiplier output current below 300 m a, r4 should be set to 1m w , meaning i ac rms varies from 95 m a to 270 m arms. the previous equation gives: i mult # 60 m arms with vin=95vrms and pout=1400w, or vin=195vrms and pout=3000w. current amplifier section: using a low r dson power mosfet as current sense instead of a resistance leads to a reduction of the parasitic inductance and allows the heat generated to be dissipated in the heatsink. using the specifications of the sth80n05, r sense max is 11m w at 25c and 15m w at 80c.
7/9 AN829 application note then the maximum rms voltage across the sense is: rms sense voltage = 15m w 16a = .24v then r8 = r9 = .24v / 60 m a # 4k w critical current amplifier gain occurs when the current error amplifier slope exceeds the osc illator sl ope. this condition occurs when: v oca f s = (v o /l b ) rsense g ca g ca = current amplifier gain v oca = current amplifier output voltage f s = switching frequency l b = boost inductor value then g ca = v oca f s l b / (v o r sense ) = 5 45e+3 0.8e-3 / 400 0.015 = 28 setting g ca # 25 enables the calculation of r z and c z : r z # g ca r9 # 100k w c z = 1 / 2pfcrz with a crossover frequency fc of 10khz. then c z =150pf. capacitor c p can eventually be added to reduce the phase lag of the amplifier. implementation and switching behavior using a double-sided pcb significantly reduces the parasitic inductances of the circuit: C parasitic inductance lp1 and lp2 shown in figure 1 are intrinsic characteristics of the isotop module itself; these values are very low (less than 10nh). C parasitic inductances lp3 and lp4 are due to the isotop/capacitor loop. the proposed layout re- sults in about 20 nh for lp3+lp4. these values mean that the total voltage overshoot during the turn off of the mosfet is limited to about 30v with a di/dt of 1000a/sec with no snubber. C parasitic inductance lp5 is a few nh due to the use of an active current sense in a to- 218 package. this results in an excellent signal/ noise ratio at the current error amplifier input. the following mea- surements have been made with the iron powder inductor as described in paragraph 4. figure 5 shows the most important signals with an input voltage of 208vac and an output power of 1600w. to show the current ripple more clearly, one second persistence has been used. the slight overshoot of the current error amplifier output during the mains zero voltage crossing is due to the rise of the inductor permeab ility at low induction. indeed, the inductor size optimisation requires operation with 50% saturation of the iron at maximum peak current. figure 6 shows average values of the waveforms in figure 5. figure 7 shows the input current and voltage with 120vac mains and 1600w output power. figure 8 shows the drain voltage and source current during turn off. note that the source current probing cre- ates a parasitic inductance, limiting the di/dt. thus there is no significant turn off overvoltage. figure 9 shows the diode recovery current with a forward current of 20a and a di/dt of 700a/ m sec. note that the r gn gate drive resistance can be adjusted to tightly control the di/dt. this is still acting with high di/dt value due to the low parasitic inductance of the gate drive. thermal measurements have been performed enabling the
AN829 application note 8/9 junction temperature to be accurately estimated: with : v in = 220vac/i in = 8arms v out = 400vdc/r gn = 0 w mosfet+diode conduction losses = 10w mosfet+diode commutat. losses = .52w/khz with: v in = 120vac/i in = 15arms v out = 400vdc/rgn = 0 w mosfet+diode conduction losses = 40w mosfet+diode commutat. losses = .88w/khz with a gate drive resistance r gn =102, 25% must be added to the commutation losses. figure 5. current & voltage recorders- figure 6. average current & voltage- figure 7. average current & voltage- figure 8. turn off mosfet behavior- figure 9. diode recovery current current amplifier output (1v/div) voltage error output (1v/div) rectified mains voltage(50v/div) instantaneous inductor current (2a/div) d95in256a 1msec div average current amplifier output (1vdiv) voltage error output (1v/div) rectified mains voltage (50v/div) average inductor current (2a/div) d95in257a 1msec div rectified mains voltage 50v/div average inductor current 5a/div d95in265a 1msec div turn off source current (5a/div) turn off drain voltage 50v/div(-100v offset) d95in266a d95in267a 20nsec div 5a/div
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 9/9 AN829 application note conclusions this paper presents an optimized power factor corrector built around a power module driven by the l4981 con- trol ic. this ste36n50-dk isotop power module is mounted directly on the pcb providing both very low in- ductance layout and compact hardware. eliminating parasitic inductances enables tight control of switching di/dt and prevents turn off overvoltage. therefore faster switching speeds are allowed to reduce switching losses. the 2amps current capab ility of the controller is also a useful feature. combined with a single layer winding inductor, such a configuration results in very low emi and rfi generation. finally, there is potential for further improvements using two features of the l4981: C the possibility either to synchronize the ic with an external signal, or to modulate the pfc switching frequency to spread the rfi noise. C the extra multiplier input, which enables external compensation.
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